4050 Non Inverting Hex Buffer

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Tommy volts
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4050 Non Inverting Hex Buffer

Post by Tommy volts » Thu Nov 30, 2006 1:07 pm

Dear forum members,

Please consider my question below:

Can a single output from a 4050 Non Inverting Hex Buffer power all six inputs (inputs tied together) of another 4050 Non Inverting Hex Buffer?

Supply voltage for both buffers will be 4.5 volts.


Thank you.

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GoingFastTurningLeft
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Post by GoingFastTurningLeft » Thu Nov 30, 2006 2:07 pm

What is the application where you'd have to put two buffers together?

The spec you're looking for is the Fanout... which I didn't see on there. At the beginning it mentions the TTL driving fanout is 2 per output, but doesn't call it fanout. I believe TTL needs more power than CMOS so it might be possible to drive 6 CMOS inputs (as in another 4050), don't know though. I guess you'd have to look at the output current maximum (i think it was 12mA) and divide that by 6 (2mA) and see if that's higher than the minimum input current.

I guess the easiest way to see if it works is to actually hook them together, but i'm guessing you are designing something and don't have them yet.

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philba
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Post by philba » Thu Nov 30, 2006 3:44 pm

I believe the 4xxx series can drive 6 4xxx loads. Input current is like 1 uA, but..

why use 4xxx series logic at all? 74HC is all around better at that supply voltage.

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ecerfoglio
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Post by ecerfoglio » Fri Dec 01, 2006 6:27 am

Looking at the datasheet ( http://www.fairchildsemi.com/ds/CD%2FCD4049UBC.pdf ), the 4050's output can sink 5 mA and source 1.6 mA (typical values @ 25°C).

Its max. input current is 1 microA, which gives a DC fanout of :shock: :shock: over 1600 driven devices :shock: :shock:

Of course, AC fanout is lower due to the input's capacitance.

In the datasheet, propagation delay times are measured with a 50 pF load, and each input has a typical input capacitance of 5 pF @ 25 °C, which gives a fanout of 10 driven inputs.

So if your application uses high frecuencies and the propagation delay is critical, or if you expect higher temperatures (see the values for 125°C in the datasheet), limit the a fanout to 6 to 10 driven inputs for each output.

But for "slow" applications (lower frecuencies or even DC, non critical timing) the fanout limitation should seldom be a limmiting factor in CMOS to CMOS logic.

What is the application where you'd have to put two buffers together? (GoingFastTurningLeft)
It's ussual to paralell CMOS buffers to make a "high current" driver to power leds, relays, small motors, etc.
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Tommy volts
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Post by Tommy volts » Fri Dec 01, 2006 8:20 am

GoingFastTurningLeft

My application is a sequential controller:

Each of the 3 outputs from a 74HC/HCT93 Modulo 8 binary counter will be connected to it's own hex buffer. 6 outputs from each buffer (now 18 total outputs) will then be tied to various inverters and triple input quad AND logic gates. The system will control a sequence of 7 different operations that will occur as the counter counts from 000 to 111.

I will also be throwing in a lot of LED indicators in parallel with various outputs. I don’t want to have to worry about source currents, sink currents, noise margins, etc, that’s why I am hoping that by using a lot of buffers I can power this thing up and have it work.


Philba

I will take your advice and use one of these buffers instead:

http://academics.vmi.edu/ee_dl/IC%20Spe ... 4hc244.pdf
http://www.cl.cam.ac.uk/Teaching/2003/H ... 4hc541.pdf

ecerfoglio

The frequency will be about 0.3 Hz, very slow. Thanks for the info, I feel more confident that it may work.

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GoingFastTurningLeft
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Post by GoingFastTurningLeft » Fri Dec 01, 2006 9:07 am

ecerfoglio wrote:Looking at the datasheet ( http://www.fairchildsemi.com/ds/CD%2FCD4049UBC.pdf ), the 4050's output can sink 5 mA and source 1.6 mA (typical values @ 25°C).

Its max. input current is 1 microA, which gives a DC fanout of :shock: :shock: over 1600 driven devices :shock: :shock:

Of course, AC fanout is lower due to the input's capacitance.

In the datasheet, propagation delay times are measured with a 50 pF load, and each input has a typical input capacitance of 5 pF @ 25 °C, which gives a fanout of 10 driven inputs.

So if your application uses high frecuencies and the propagation delay is critical, or if you expect higher temperatures (see the values for 125°C in the datasheet), limit the a fanout to 6 to 10 driven inputs for each output.

But for "slow" applications (lower frecuencies or even DC, non critical timing) the fanout limitation should seldom be a limmiting factor in CMOS to CMOS logic.

What is the application where you'd have to put two buffers together? (GoingFastTurningLeft)
It's ussual to paralell CMOS buffers to make a "high current" driver to power leds, relays, small motors, etc.
Makes sense, You learn something new every day.

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philba
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Post by philba » Fri Dec 01, 2006 10:35 am

sounds good tommy. just keep in mind the total current of the chip for the HC series. While a single pin can do up to something like 35 mA, 6 or 8 times that will be well about the chip max current. You can factor in duty cycle. Also, don't forget to consider thermal issues as the DIPs and SOICs don't do so well there.

On paralleling to get more drive - yeah, that's a common technique but only within a narrow range. You are better off using a transistor, darlington or mosfet for higher current needs.

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Post by haklesup » Sun Dec 03, 2006 6:19 am

the 4000 series CMOS is great if you have a variable supply voltage (as in batterypowered) or for some reason don't want to use 5V logic.

The 74HCxx and 74HCTxx is better if you have to drive a bigger load and the 74ACTxx has even more powerful outputs. All have very low current inputs (<100nA I know from curve tracing, dispite the max rating in the datasheet) Since you want to put LEDs in here and there, use the74HCT or else youwon't have much current available to bias the LED and still maintain the logic level. Furthermore the 74HCT is more balanced WRT source and sink current so you can use positive or negative logic to light the LED. You'll want a current limiting resistor with the LED to keep the chip IDD down as Philba suggested.

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