lowering the output voltage question

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mikeb
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lowering the output voltage question

Post by mikeb » Thu Oct 02, 2003 4:47 pm

im using to different circuit boards run from 2 different power sources board1 has a vdd of 5volts and board2 has a vdd of 3.3 volts. board1 outputs are connected to the inputs of board2. the outputs when high from board1 are at 5 volts the inputs of board2 can only be as much as 3.3 volts when the input is high the low output from board1 is compatablie with board2 but i need a circuit that will lower the voltage when the outputs are in a high state (logic1) at board1, to 3 to 3.3 volts,so that the outputs of board1 are compatablie with board2.any advice will be appreciated.

bodgy
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Re: lowering the output voltage question

Post by bodgy » Thu Oct 02, 2003 8:30 pm

Sorry , I haven't answered your PM.<p>One way would be to have a transistor with the collector connected to the lower voltage - problem here is that the pulse will be inverted, though nothing apart from extra current draw to stop you having two inversions. I suppose you could just take the feed from the emitter instead, there'd be a problem here, just can't think what it is at this moment.<p>A CMOS non inverting gate that can take 5v on its inputs while running from 3.3v supply.<p>A 3.3v zener diode.<p>Colin
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Bernius1
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Re: lowering the output voltage question

Post by Bernius1 » Fri Oct 03, 2003 4:17 am

I remember there was once a series of buffer / bus chips ( Chip the bus driver ? ) years ago that were specifically made to adapt TTL to CMOS. Check your 7400 series books, or try the buffer with a lower supply, like bodgy said.
Or a reverse-biased diode as a clamp, but if it pulls everything high, you'd need inverters, and it'll slow down a bit.
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Chris Foley
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Re: lowering the output voltage question

Post by Chris Foley » Fri Oct 03, 2003 6:23 am

If you're not interested in high speed, your best/cheapest choice would be the CD4504 CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation. It will work well for one-way translation of 5V logic signals (either TTL or CMOS) into CMOS-level signals. On the chip, connect Vcc to your +5V, and connect Vdd to your +3V, and you're done. Pinout is a little inconvenient, but just read the data sheet, and you'll do fine. Also, at 3V operation, I wouldn't guarantee this at much more than 1 or 2MHz. Again, check the data sheet.<p>CD4504 Data Sheet.pdf<p>Good luck.
Chris<p>[ October 03, 2003: Message edited by: Chris Foley ]</p>

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