Pulse Generation

[Sambuchi]

Hello all. I have a question for the experts here.

I need a circuit that can generate a 5V 50ns pulse every 90us

Whats the best way to do this?

Thanks in advance!

Tony

[Bob Scott]

Hi Sambuchi.

That would be 11,111 Hz with a 0.0555% duty cycle.
It looks like you need an oscillator or astable multivibrator with a very low duty cycle.
What is the available power supply voltage?
What are the load requirements? (voltage, current drive)
How accurate does the timing of the pulses need to be? (frequency, tolerance)
How square do the pulses need to be? (Critical rise/fall time?)
Is any particular logic family involved?

I would think that the 555 timer might be suitable, or a multivibrator using logic gates.

[Robert Reed]

As Bob said, need more info as to error limits on the final pulse. But if this does not need to be laboratory grade then you could acheive this very simply cheaply with one 74 HC quad Nand gate. Two gates form an astable at somewhat over 10 KHz. Third gate is a simple one shot driven from the astable and thru a differentiating network. Fourth gate is a bonus - for inversion if desired or whatever. Parts- one cheap HC Mos nand gate , 1 1N914 diode , 3 ceramic caps of lo value and three 1/4w resistors. Certainly less than $1 for the whole shebang. Add some pots and also make it variable if desired!

[MrAl]

Hi,

Robert:
I am wondering now too what the accuracy has to be for his circuit as that is going to affect the
design quite a bit. I also wonder what this is going to be used for as there may be other
solutions altogether as well.
Hope he gets back here with some answers.

[Sambuchi]

Thanks for the input everyone. This circuit will be used to test an amp circuit. For the accuracy question I would say it would have to be fairly accurate. I am testing the threshold of the data transmission and would like to meet the spec as much as possible. Bob & Robert, thanks for the great input. I think I may have to look into a circuit as you described.

This test circuit had me go down an interesting path of PLD's from ATMEL. I think I'm going to start a different topic for it!

[Robert Reed]

The circuit I described when operated in a R.T. environment and fed by a good regulated supply should hold an accurracy of 1% (I think). let us know what your requirements are.

[MrAl]

Hi again,


Another idea i though of is to use a 20MHz crystal or oscillator for the clock, and a flip flop first to divide by 2
(10MHz fairly clean and 50 percent duty cycle) along with some discreet logic counters (or LSI counter) to
divide by the correct count in order to get your lower frequency pulse spacing. At the end of the count,
one pulse would be gated to the output at which time the count would start all over again.

Too bad a run of the mill uC would be a bit hard to use for this because the pulse width is so short.
50ns is quite short, are you sure you really need that short of a pulse width? If you could get away
with say 200ns (four times as long) you could use a very cheap uC chip with a 20MHz crystal and
you'd be done.

[Sambuchi]

I will need the pulse to be 50ns unfortunately. I will have some time this week to review all of this great data and then make a decision on what is practical for my testing needs.

Thanks again everyone.