I am wrapping up my first digital design class which used the Nexy’s FPGA. Unfortunately the professor never got into practical applications or real world scenarios. I am curious as to how FPGA’s and similar devices like CPLD’s are used in industry, and why they would be chosen over microcontrollers.
Also, since my knowledge of microcontrollers is pretty sketchy as well, what are the major software and hardware differences between a microcontroller and a FPGA?. It is my understanding that a microcontroller can be made from a FPGA, but I have to wait till the fall to learn about that.
Thanks
FPGA vs Microcontroller
Designing with a uController is fairly generic and that chip often requires a mess of other peripheral chips like memory or interface chips and app specific circuits to complete the job. There are many uControllers with all manner of options built in but they still may not have all the functionality you need in one package. Especially if you are doing any DSP.
That's fine if you're making a good margin and not too many but what if you are making a very high volume lightweight portable device. Now it might make sense to pay for all that NRE, licensing, design tools and proto chips. An FPGA solution can often reduce several chips into one at a lower per unit cost. Once the up front is paid, you can make your product for lower cost.
Like life, in electronics there is almost always more than one way to do it. Your job is to find the most profitable way.
That's fine if you're making a good margin and not too many but what if you are making a very high volume lightweight portable device. Now it might make sense to pay for all that NRE, licensing, design tools and proto chips. An FPGA solution can often reduce several chips into one at a lower per unit cost. Once the up front is paid, you can make your product for lower cost.
Like life, in electronics there is almost always more than one way to do it. Your job is to find the most profitable way.
A microcontroller does a series of steps -- usually one at a time -- to complete some task. An FPGA is just a way to wire up logic circuits that "do something".
Consider a simple example. Suppose we are working on, say, a rocket engine. We need to monitor 32 sensors and decide if any of two of them are out of limit. If they are we need to assert a shutdown as fast as we can.
There are ways you could design this with a microcontroller, but for illustration's sake I'm going to make it as hard as I can
Suppose each sensor is a 12 bit A/D that you read via a parallel register scheme.
A typical microcontroller would do this:
1) Read sensor #1
2) Test the limit
3) If limit exceeded twice set output
4) Repeat for sensor #2 (and so on)
So it is going to take 96 high-level steps to do the job and each step is probably several machine instructions. So if the CPU has a cycle time of 1uS, you are probably still in the millisecond range for all the sensors to be checked. What's more if sensor #1 and sensor #32 are out of limit, it could be a whole mS before you figure that out (assuming you found #1 out of bounds first).
For many tasks that might be good enough. But what if our design called for detecting faults within 5uS? Well you could speed up the processor, but you have to speed it up A LOT because the cycle speed is only 1/1000 or so of the total loop time.
Another option would be to use an FPGA. Assuming enough I/O, each A/D could get a dedicated port. It would be easy to detect any two faults and then the timing would depend on the FPGA's gate delay which is very small times the length of the longest logic path which is very small. It would be very easy to meet the strictest timing requirements with such a system.
Now, the modern thing to do is to have a CPU with an FPGA (or design a CPU using logic and program it into the FPGA). So, for example, if I were really doing this, I might put a simple CPU on the FPGA and then my "logic" part would just read the A/D, test the limit, and set a 32-bit word with the status that the onboard CPU could read. Since the CPU is just some FPGA gates, I could add a custom instruction that would look for more than one bit being set in a 32-bit word. So now I'd have a very small fast program that I could easily change (to set 2 outputs, for example, or maybe require the 2 faults to stay set for a certain length of time, etc.). But I'd have "hardware assist" to make my timing requirements.
This isn't much different from, say, a PIC where the CPU gets help from things like timers, A/D, PWM generators, etc. except with the FPGA you design and install the helper devices you need. Which, of course, is also more work for you, but you get what you want. One of the fundamental trades in life!
Oh yeah, I almost forgot. If you want some FPGA/CPLD tutorials (along with some CPU tutorials) you might enjoy http://tutor.al-williams.com. [/url]
Consider a simple example. Suppose we are working on, say, a rocket engine. We need to monitor 32 sensors and decide if any of two of them are out of limit. If they are we need to assert a shutdown as fast as we can.
There are ways you could design this with a microcontroller, but for illustration's sake I'm going to make it as hard as I can
Suppose each sensor is a 12 bit A/D that you read via a parallel register scheme.
A typical microcontroller would do this:
1) Read sensor #1
2) Test the limit
3) If limit exceeded twice set output
4) Repeat for sensor #2 (and so on)
So it is going to take 96 high-level steps to do the job and each step is probably several machine instructions. So if the CPU has a cycle time of 1uS, you are probably still in the millisecond range for all the sensors to be checked. What's more if sensor #1 and sensor #32 are out of limit, it could be a whole mS before you figure that out (assuming you found #1 out of bounds first).
For many tasks that might be good enough. But what if our design called for detecting faults within 5uS? Well you could speed up the processor, but you have to speed it up A LOT because the cycle speed is only 1/1000 or so of the total loop time.
Another option would be to use an FPGA. Assuming enough I/O, each A/D could get a dedicated port. It would be easy to detect any two faults and then the timing would depend on the FPGA's gate delay which is very small times the length of the longest logic path which is very small. It would be very easy to meet the strictest timing requirements with such a system.
Now, the modern thing to do is to have a CPU with an FPGA (or design a CPU using logic and program it into the FPGA). So, for example, if I were really doing this, I might put a simple CPU on the FPGA and then my "logic" part would just read the A/D, test the limit, and set a 32-bit word with the status that the onboard CPU could read. Since the CPU is just some FPGA gates, I could add a custom instruction that would look for more than one bit being set in a 32-bit word. So now I'd have a very small fast program that I could easily change (to set 2 outputs, for example, or maybe require the 2 faults to stay set for a certain length of time, etc.). But I'd have "hardware assist" to make my timing requirements.
This isn't much different from, say, a PIC where the CPU gets help from things like timers, A/D, PWM generators, etc. except with the FPGA you design and install the helper devices you need. Which, of course, is also more work for you, but you get what you want. One of the fundamental trades in life!
Oh yeah, I almost forgot. If you want some FPGA/CPLD tutorials (along with some CPU tutorials) you might enjoy http://tutor.al-williams.com. [/url]
I got a board some time ago for $99 from a Chinese company on eBay. The board looked cool and I could not resist the price.
Development was via Quartus (this was an Altera Cyclone 2 FPGA) and that is easy but the product of your hours of hard work is not comparable to what a Parallax board, for example, would produce.
What compensates for such lack of sexy output is speed.
Speed and concurrent (not like serial mult-tasking, preemtive blah blah) tasking. I do meen parallel events occuring on the same clock edge. That is cool but for what I was doing, not really helpful...
B
Development was via Quartus (this was an Altera Cyclone 2 FPGA) and that is easy but the product of your hours of hard work is not comparable to what a Parallax board, for example, would produce.
What compensates for such lack of sexy output is speed.
Speed and concurrent (not like serial mult-tasking, preemtive blah blah) tasking. I do meen parallel events occuring on the same clock edge. That is cool but for what I was doing, not really helpful...
B
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