fast high current transistors

[Ron H]

Windmiller, if I understand you correctly, you are taking the output from the emitters. You won't get inversion at the emitters. I belive that what you have described is a push-pull emitter follower. Have I misunderstood your circuit description?

[fsdenis]

RonH:<p>You are correct. I am taking output from the emitters and there is no waveform inversion compared to base-emitter voltage.<p>The inversion I meant to indicate is that the
current in the one ohm resistor from emitters to
neutral 0v between +5v and -5v rails is reversed in direction depending on whether the npn or the pnp is turned on.<p>The current direction reversal is useful in driving transformers and in driving large transistor array base-emitter junctions hard-on and hard-off.

[fsdenis]

RonH:<p>Is there language that makes clear whether one is talking about voltage inversion in an amplifier or about power inverters?

[fsdenis]

Al Sekeet:<p>Thanks for the suggestions. I've written them down
for further study and experiment.<p>The notion of saturation of the base-emitter junction keeps coming up. It seems related to the
notion of storage time. I've had a little time for
further study and digestion of comments so far.
Maybe some of my puzzlement is at least getting
clear enough to ask better questions:<p>1) On my bench I can turn on the n=20 tip41c array with the fast inverter in what seems to be less than .1 microseconds. But, when I turn it off, I see a delay of about 3 microseconds before
collector-emitter current actually stops. I understand that this delay is called storage time.<p>What accounts for the difference in time it takes to turn the transistors off versus on?<p>Is a large base-emitter capacitance created when a
transistor is on and uncreated when the transistor is off?

[Chris Smith]

Most power fets arent static sensative these days, and dont pop just looking at them. 250 ns is easy for the modern power Fet, and 8 amps is easy.<p> However, a warning to your volt meter, never comnnect it to the out put of high voltage of 100 volts or so, at extreame speeds of mega hertz. <p>The voltage will walk right up the circuit board like a tesla coil, and fry everything. <p>Surface tension breaks down at high frequency, and current flows on the out side of things rather than inside the wire. I toasted one of my meters at 120 volts, at several [50] mega htz.

[fsdenis]

Chriss Smith:<p>Thanks for your comment. Has there been a "b" version of power fets developed similar to CMOS "b"?

[chessman]

<blockquote><font size="1" face="Verdana, Helvetica, sans-serif">quote:</font><hr>Originally posted by Chris Smith:
However, a warning to your volt meter, never comnnect it to the out put of high voltage of 100 volts or so, at extreame speeds of mega hertz. <p>The voltage will walk right up the circuit board like a tesla coil, and fry everything. <p>Surface tension breaks down at high frequency, and current flows on the out side of things rather than inside the wire. I toasted one of my meters at 120 volts, at several [50] mega htz.
<hr></blockquote><p>
I can attest to that! In my stupidity I connected a bench meter to the output of a blacklight inverter!!<p>All I can say is, thank god for fast-acting fuses...<p>The sparks were pretty cool though.<p>Not as cool as earthing the neutral and hot feeds of a mains line together.....

[Ron H]

<blockquote><font size="1" face="Verdana, Helvetica, sans-serif">quote:</font><hr>Originally posted by windmiller:
Al Sekeet:<p>Thanks for the suggestions. I've written them down
for further study and experiment.<p>The notion of saturation of the base-emitter junction keeps coming up. It seems related to the
notion of storage time. I've had a little time for
further study and digestion of comments so far.
Maybe some of my puzzlement is at least getting
clear enough to ask better questions:<p>1) On my bench I can turn on the n=20 tip41c array with the fast inverter in what seems to be less than .1 microseconds. But, when I turn it off, I see a delay of about 3 microseconds before
collector-emitter current actually stops. I understand that this delay is called storage time.<p>What accounts for the difference in time it takes to turn the transistors off versus on?<p>Is a large base-emitter capacitance created when a
transistor is on and uncreated when the transistor is off?<hr></blockquote><p>A bipolar transistor is saturated when the collector-base junction is forward biased. When this happens, excess charge (beyond that required to saturate the transistor) accumulates in the base region, and must be cleaned out before the transistor can turn off. A Baker clamp works by not allowing the c-b junction to be forward biased. You can also think of it as nonlinear negative feedback which is applied only when the collector-base voltage gets below a certain point.<p>To turn off a saturated transistor rapidly, you have to apply reverse base current for enough time to clean out the excess charge. The more current you apply, the quicker it will turn off. If you have a series base resistor driven by a low impedance, you can put a small value cap across it to suck out the charge. This will also generally improve the turn on time somewhat. If you are driving the base with a high impedance(switched current source), you can apply reverse current with another switched current source, or a fixed resistor to a negative voltage, for quicker turn off. In either case, it is sometimes necessary or at least helpful to put a diode across the b-e junction, connected so that it clamps the reverse base bias when the base is being cleaned out.
Breadboarding is the best way to experiment with these techniques, but not the quickest or safest (for your trannies). I use Linear Technology's SwitcherCADIII for simulations. It is free and is not castrated, hamstrung, or whatever, as is the case with most other free versions of Spice.<p>Ron<p>[ April 28, 2003: Message edited by: RonH ]</p>

[russlk]

Re: your question about time difference turning on versus turning off: When the transistor is turning on, the collector voltage is high and the collector-base capacitance is low. It is only necessary to charge up the base-emitter junction capacitance to get it turned on. When the transistor in ON (saturated), the base-collector junction is forward biased and the capacitance is high. It is necessary to discharge the base-collector junction and that takes a relativly long time. one way to avoid saturating the collector is to use a diode feedback from the collector to base bias so the drive is turned off when the collector gets down to the level of the base voltage. This probably has a name, but I don't remember.

[Chris Smith]

Fets have come a long way in the last ten years. Most have a surge suppression circuit built into the gate, with up ward voltage suppression of 100 volts or more with out compromising the switching speeds or capacitance at the gate. Check into the several companies including the lighting company that specializes in Fets for fluro lighting, called I believe "lights on" or something like that? I have several other names, hidden in my many tens of thousands of files, so It’s a little hard to access any in a hurry.<p>On the volt meter with the HV-High freq, the whole circuit plane glows blue when you screw up like something out of a Frankenstein movie or a Jacobs ladder?

[fsdenis]

Ron and Russ:<p>Thanks for the clues. <p>I read of unsaturated and saturated operation of
bipolar transistors. Perhaps "saturation" has
more meanings than base-emitter saturation?<p>On my bench I see three very different modes of
operation of the tip41c (and other) transistors.
1) Rce = m1 * Ib + b1 (nearly linear and almost constant) where the collector-emitter resistance is about .2 ohms max and INDEPENDENT of Ic to Ic of at least 2 amps with Ib = 60 ma.<p>2) Ic = m2 * Ib + b2 (also nearly linear and almost constant). This apparently what is meant by
beta gain.<p>3) there is a morphing region between these different modes that I haven't described by a formula.<p>The first of these modes where Rce is roughly constant and Ic up to about 2 amps has no influence on Rce is, maybe, called unsaturated operation. The second is called saturated operation. the morph isnt called anything.
The language here seems different from base-emitter saturation. Maybe? What?

[fsdenis]

On my bench, I see that 20 tip41c transistors in parallel with 60 ma Ib for each transistor gives me a total parallel Rce of (max) .2ohms/20.<p>At a total Ic of 35amps, I measure Vce of less than .3volts.<p>And any Ic from 0 to well past 35amps does NOT
change or influence total Rce.<p>This ability to switch large currents quickly and
be able to just treat the transistor array as a
very small resistor when on is why I am pursuing
parallel transistor arrays.<p>The storage time for the entire array is about the
same as for an individual transistor.<p>A smaller transistor (2n4401) has a very short storage time compared to the tip41c. When paralleled, the storage time stays short. And I
may also treat the array as a small value resistance when on. And this Rce is not changed
or influenced by Ic from 0 to more than 200ma per
transistor in parallel with Ib to each at about 13ma.<p>These notes might make it easier to see where my confusions vs language might be getting in my way.

[fsdenis]

Chris Smith:<p>Thanks for the fet hints indicating they might not
be as easy to destroy as they were (about 15 years ago) when I last tried them.<p>I, too, have a filing system similar to a black hole. Nothing comes out easily.