78L05

[Turbo46]

Hi<p>Im currently using a 78L05 chip to power up my PIC 16C773 and my 231CPD driver/ reciver chip. The circuit functions ok when running, but the circuit is real hard to boot up. When the circuit is connected to Hyper-terminal when phalse boots occur junk comes through.<p>The 78L05 is fead with 12V DC on the input and has a 10uF polarised cap accross this input to ground. When i disconnect this cap the booting becomes impossible and the junk on hyper-terminal is worse. Therefore if i say put a 100uF cap in place of my 10uF, would this solve all my problems? If so what is the maths behind it, or is it just a plug and play theory?<p>After reading through a few of my monthly issues of practical electronics, i notice that most of the circuits that they build us 100uF! Is this the reason why they use them?<p>Cheers Turbo46

[Dean Huster]

Well, with the cap disconnected, this means that you have absolutely nothing on the input, so don't do that. Even with a clean wall-wart, the cap should be there. You didn't mention the 5v output. Do you have a cap there, too? I hope so. If not, try putting a 0.1µF ceramic cap in parallel with a 10µF cap from the 5v output to ground and see if that fixes your woes.<p>Dean

[Turbo46]

yeah i habe a 0.1uF cap on the output. I have just read 2 different 78L05 data sheet and they both have different input caps. The national semiconductors sheet says use a 0.33uF cap.<p>Which way would you guys go, up or down? Or just plug and play and see what happens?<p>Cheers Turbo46

[philba]

larger. Here's how I would do it.<p>Your 12V DC wall wart probably puts out around 17VDC peak (1.414 * 12). You want solid DC input of around 8V to the 78L05. So lets say around 9V of ripple to get rid of. Lets say your circuit pulls 100 mA. The filter cap gets charged 120 times a second for an 8.3 mS period. Using C = (I * T)/Vripple I get about 925 uF. Use a 1000 uF filter cap.<p>If you use smaller wall wart, like 9V you can reduce the cap. exercise left to the reader.

[Ron H]

<blockquote><font size="1" face="Verdana, Helvetica, sans-serif">quote:</font><hr>Originally posted by philba:
larger. Here's how I would do it.<p>Your 12V DC wall wart probably puts out around 17VDC peak (1.414 * 12). You want solid DC input of around 8V to the 78L05. So lets say around 9V of ripple to get rid of. Lets say your circuit pulls 100 mA. The filter cap gets charged 120 times a second for an 8.3 mS period. Using C = (I * T)/Vripple I get about 925 uF. Use a 1000 uF filter cap.<p>If you use smaller wall wart, like 9V you can reduce the cap. exercise left to the reader.<hr></blockquote><p>I think you slipped a decimal point there. I get 92uF.
Every DC wall wart I've seen already has a filter cap which provides reasonably low ripple at rated current. That doesn't mean that a cap near the regulator will not be required for stability.
Lastly, a lower voltage wall wart will require more capacitance (not less, as you suggested), because the ripple has to be less in order to maintain headroom for the regulator..<p>[ February 08, 2005: Message edited by: RonH ]</p>

[Mike6158]

<blockquote><font size="1" face="Verdana, Helvetica, sans-serif">quote:</font><hr>Originally posted by philba:
larger. Here's how I would do it.<p>Your 12V DC wall wart probably puts out around 17VDC peak (1.414 * 12). You want solid DC input of around 8V to the 78L05. So lets say around 9V of ripple to get rid of. Lets say your circuit pulls 100 mA. The filter cap gets charged 120 times a second for an 8.3 mS period. Using C = (I * T)/Vripple I get about 925 uF. Use a 1000 uF filter cap.<p>If you use smaller wall wart, like 9V you can reduce the cap. exercise left to the reader.<hr></blockquote><p>?? Looking in my ARRL Handbook... I see C x E = I x t where:
C- Capacitance in µf
E- peak to peak ripple voltage
I- Load current in mA
t- Time between half cycles of the rectified waveform in ms. For 60Hz full-wave rectifiers this is about 7.5 ms. <p>Naturally I have some questions. For one... why is the period for 60Hz 7.5 ms in the handbook and 8.33ms in your example? I also got 8.33 by taking .5/60 or 50% of the cycle / cycle. 7.5ms works out to about 90% of 8.33ms.<p>When I work thru the formula using your values I don't get the same number. Where am I going wrong?
C = IT/Vripple so:<p>(100 x 8.33)/9 = 92.5555 or 1/10th of the value that you got. That tells me that I have a units problem somewhere but I can't find it.

[Ron H]

<blockquote><font size="1" face="Verdana, Helvetica, sans-serif">quote:</font><hr>why is the period for 60Hz 7.5 ms in the handbook and 8.33ms in your example? <hr></blockquote>
Well, the period IS 8.33ms, but, due to droop, the rectifier will start to conduct before the peak of the next half cycle. The exact time depends on the amount of droop, which is in turn dependent on load current and capacitor value. I usually use 8ms, because it takes a couple less key strokes, and filter capacitors have very loose tolerances, so it ain't critical unless you're calculating worst case.
And you aren't the one with the units problem. See my previous post.<p>[ February 08, 2005: Message edited by: RonH ]</p>

[philba]

Yup, used .083 S instead of 0.0083. I was rushing out the door and didn't double check it. thanks for catching that and being so gracious.<p>Some wall warts are pretty bad on filtering, I've put a couple on my scope and been suprised how much ripple is there. The littler ones seem to have less to no filter caps. I would not skimp on one in my circuit.<p>Several other points/questions -
I assume by 231CPD you mean a max231. How are you getting the 7.5 - 12V to it? is that power clean?<p>I'd use a smaller wall wart (9V or even 7) because the 78L05 is unnecessarily dissipating over half the input as heat and you really want that part to run cool. Especially with the 231 which I believe can pull in the 30-50 mA range. (I had a max232 that pulled over 70 mA even though the spec implies that short circuit output is around 55 mA).<p>What else do you have in your circuit? The 78L05 is max rated to 100 mA but I wouldn't get that close - maybe 75 mA or so. The to92 case really isn't very good a dealing with heat. Max specs have little gotchas like "at 70F ambient" and such. Given your rs232 driver and the PIC, anthing else may push you over the edge. Have you checked the temperature?<p>Do you have the power up timer of C773 enabled? its a good idea to do that to let the voltage fluctuations settle out.<p>[ February 08, 2005: Message edited by: philba ]</p>

[rshayes]

First, you may want to change the regulator to a heavier version in a TO-220 package. The TO-92 package will not dissipate more than a few hundred milliwatts before heating to the point where the regulator will reach its temperature limit. This may occur with laod currents above 20 milliamps or so with the TO-92 package. If needed, it is also easier to add a heatsink to the TO-220 package.<p>I usually put a .1 uF ceramic capacitor on both the input and output of a three terminal regulator. These should be as close to the package as possible. These capacitors are to provide a good bypass at high frequencies. The transistors in the regulator have substantial gain well into the megahertz region, and thus the potential for oscillation.<p>In addition, I usually put at least a 10 uF electrolytic on the output. This is to provide a low impedance in the 100 KHz range. On the input side, I also usually put a 10 to 100 uF electrolytic capacitor unless there is already a large capacitor nearby. This is to control the impedance seen by the regulator at intermediate frequencies. This may be overkill, but at low impedance levels several inches of wire can have significant amounts of stray inductance. The basic idea is to give AC currents a low impedance path to ground in the local area so that conditions elsewhere are not significant.<p>[ February 09, 2005: Message edited by: stephen ]</p>