Switch debouncing

[haklesup]

Your comments please:<p>I'm designing a simple 2 digit counter circuit based on the CMOS 4518 BCD counter and 5411 7-segment decoder ICs. The input will come from a momentary pushbutton at the end of a long cable. The whole thing is powered to 12V.<p>I am accounting for EOS and ESD by putting double diodes (clamping) on the board at the end of the cable but there still remains the issue of preventing double counts due to switch noise.<p>My first instinct was a series resistor and cap to ground but then I saw a better way in a circuits book. Currently I plan to use a 555 timer configured as a one shot multi vibrator (bounceless switch).<p>My question is: do any of you have comments on the pros and cons of such circuits? How many other alternative debouncing techniques are there? Is there a better way? Is this even necessary?<p>This is one of those "more than one way to...." problems and it got me wondering about alternatives.

[bridgen]

I've only just registered as a user so I haven't had time to play around trying to post links to images. For that reason I have posted a possible solution on my web site at www.davidbridgen.com.
Regards.

[Joseph]

The best way I found is to use an RC timing circuit in conjunction with the switch. That way, when you press the switch, the capacitor allows only one few hundred nanosecond pulse to tranfer to the input pin of the IC. The charge and discharge constants of the timing capacitor are vastly different so that it takes much longer for the capacitor to return to its pre-pressed state once the switch is released.

[bobsRAC]

the lowpass filter is proned to making the problem worse... The lowpass makes the signal rise and fall more slowly, keeping the signal around the switching point for a longer period. any spike or noise that occurs around this region can cause another trigger.<p>The simplest scheme is a pair of inverters in series (preferrably schmidt trigger). The most effective may be the 555 monostable multivibrator.<p>[ August 25, 2002: Message edited by: bobsRAC ]</p>

[MrAl]

Hello,<p>The simplest scheme is to wire two inverters
in antiparallel and use a SPDT switch.
This provides de-bouncing no matter how
long the bounce is.
You wire the output of the second inverter to
the input of the first inverter, then the
output of the first inverter to the input of
the second inverter. You wire one pole of the
switch to the input of one inverter, the other
pole to the input of the other inverter. The
common or 'arm' of the switch goes to ground.
You also wire two pullup resistors to the inputs
of both inverter gates.
Now, when you toggle the switch to one pole,
one input gets grounded while the other input
goes high, which causes that inverter to provide
a low to the input you grounded, which keeps it low.
This action is the same as a latching type action,
so the state of the two inverters stays at whatever
state the switches' first bounce caused. Any other
bounce wont change the state, only toggling the
switch in the other direction will.<p>Another great way is to use a set/reset latch.<p>Either of these two methods will work no matter
how long the bounce period lasts.<p>--Al

[bwts]

Isn't this a classic example of what a Schmitt trigger is for?

[Ron H]

Al:
Why would you need pullup resistors, unless you were using open drain (or collector) inverters?<p>Ron

[MrAl]

Hi Ron,<p>That's both a question and an answer <p>I would prefer to use open collector devices because that would
eliminate any momentary output short to ground if a regular gate
was used. This would require pullups.<p>Since it's harder to find CMOS gates with open drains perhaps
it would be easier to cross couple a pair of nand gates to form a
latch, or use an SR latch, both of which can easily be found in
any of the cmos logic families.<p>Most of the TTL families can take a short to to ground on any one output
at a time, but it's probably better practice to use a non-shorting
technique as with the other gate ideas.<p>To make a non-output-shorting SR latch out of a CD4011 for example:
connect pin 2 to pin 4,
connect pin 3 to pin 5,
connect pin 1 to one pole of the SPDT switch,
connect pin 6 to the other pole of the switch.
Connect the arm of the switch to ground.
Connect 10k pullups to pin 1 and pin 6 (one for each pin).
Connect pin 14 to V+
Connect pin 7 to ground.
Take an output from either pin 3 or pin 4.
When the switch is toggled, the outputs change state
and are considered absolutely debounced.<p>Good luck with your circuits,
Al<p>[ September 12, 2002: Message edited by: MrAl ]</p>

[Ron H]

Well, the momentary short only lasts for the sum of the propagation delays of the two inverters, and then the output assumes the state of the switch. I can't think of a logic family where this would be a problem.<p>Ron

[MrAl]

Hi Ron,<p>I dont always think of this as a problem either,
but with the TTL LS family for example,
the spec sheet says not to short more then
one output at a time, so even though it's only
a short for maybe 50ns or so, i would rather
use another method for that family.
On the other hand, if i was pressed for
gates and i happened to have two LS inverters
left over, i'm pretty sure i would use them.
If i had the choice of what to order when dealing
with the CMOS family he seemed to be using,
i'd probably order an RS flip flop instead.<p>There is always the possiblity of using two external
2N4401 transistors of course as well.
The 'cons' to this idea is that more resistors
would be required.<p>Of course all this assumes that there is at least
an SPDT switch available to do the pulsing
If there are only SPST switches available,
that leaves us with one shot type circuits.
I was assuming that the end user had the choice.<p>
Good luck with your circuits,
Al