current mirror circuits

[jimandy]

My favorite technical reference is Horowitz and Hall (second edition), so for those of you who have a copy, look up the current mirror circuits in chapter two. Notice that they are all built around PNP transistors and show them sourcing a load. Now when I Google “current mirrorâ€

[dtief]

I'm not sure why the 2 different information sources "prefer" the different types. I have worked with circuits that use both sources & sinks.

[Bigglez]

those of you who have a copy, look up the current mirror circuits in chapter two.

And those of us that don't?

Notice that they are all built around PNP transistors
...but all with NPN transistors that sink the load.
Why is this?

Why wouldn't it be so?
A current mirror is a circuit technique that can
be build with either sex transistors.

If you try to build your own be aware that the
devices in monolithic IC form are matched and
track with temperature. Also, the size of the
transistor regions are scaled to give ratiometric
current out for a given current in.

If you decide to build your own start with an
array of matched transistors. The RCA CA30xx
family were popular for this task, and may still
be found as NOS parts.

[jimandy]

Why wouldn't it be so?
A current mirror is a circuit technique that can
be build with either sex transistors.

Yes, I see that now. I was just curious to know why more examples on the web (at least ones I find by Googling) are of the current sinking variety. To put it another way, in circuit design, is there more usefulness in sinking a load than sourcing it?

[Bigglez]

A current mirror is a circuit technique that can
be build with either sex transistors.

I was just curious to know why more examples on the web... To put it another way, in circuit design, is there more usefulness in sinking a load than sourcing it?

A big part of the answer is that NPN structures are
easier to make, have higher hFE for a given area,
are therefore smaller. In the chip business it all about
die size, and yields - but everone is now north of 90%
KGD - Known Good Die per wafer. Same holds true
for MOSFets (compare P-ch and N-ch prices).
When IC combinational logic appeared in the late '60s
(TTL for example) it was built in an NPN only process.