Gate inputs.

[mgrooms55]

I understand that an open on the input of a logic gate is read as a high by the gate. But WHY is it read as an open?<p>Thanks in adance.

[hlreed]

Logic gates are designed to be connected. An open input is not part of the logic. As to how it reads high: It probably has a weak pullup in the input to prevent it from oscillating (high,low,high,low). The data sheet, if you can even find one, might tell you.
The main thing is, connect all inputs even if they are not used.

[Ron H]

In the TTL logic families, each input has an internal pullup resistor whose current must be shunted to ground with an impedance that is low enough to bring the input voltage below the logic low threshold. This is an oversimplified explanation, but it is adequate for this discussion. As Harold said, even if you want an input to be always high, it is a good idea to tie it to VCC. Of course, if you want it to be low, the circuit will not work unless you tie it to ground or an output that is always low.<p>In the CMOS logic families, a floating input can be either high or low, depending on leakage, accumulated charge, etc. Floating inputs can, and frequently do, cause excessive current to be drawn by the device. You MUST tie unused inputs to the appropriate logic level to ensure correct operation.<p>I learned about this the hard way on my first CMOS design, which was supposed to be a low power circuit. After wirewrapping the breadboard, not only did it not work, but it drew WAY too much current. After discovering the cause of the problem, I then had to find the chips with the floating inputs. One method I used was to check the temperature of the various chips with my finger, and with a non-contacting thermometer. Most of the parts that had floating inputs actually got warm enough that you could feel the temperature difference between them and the ones that had no floating inputs. I didn't make that mistake again.<p>Ron