passive integrator design

[redrocker]

I have a reference design from a magazine article of a PWM to DC converter circuit that works well, and I would like to adapt it a different frequency, but I don't know how to.<p>The source is 5 V at 10 kHz and variable duty cycle. The load is a two-pole passive integrator consisting of a 10 k resistor and a .1 uF capacitor connected to the source, and another 10 k resistor and .1 uF cap connected to the junction of the first pair.<p>The DC output is proportional to the duty cycle. For example, if the pulse width is 40 us, the output voltage is 2 V. (2 V / 5 V) = 40 %, same as the duty cycle.<p>Clearly a relationship exists between the component values and the frequency to make the output proportional to the duty cycle. What makes this difficult is that a period of time occurs before the output resolves on the steady state output. It looks like a problem that needs a steady state analysis, but it is not using sinewaves. Does anyone have any idea how to design such a circuit?

[Ron H]

Let's call the first Resistor R1, the first capacitor C1, etc. BTW, you can get the same amount of filtering, but faster settling, by making R2=100k and C2=10nF.<p>For the analysis, assume that you have very low ripple on C1 and C2. For analyzing the voltage on C1, we can then say that no current flows through R2 compared to the current through R1, because R1 has ±5v across it, while the voltage across R2 is nearly constant. The current through R1 will be I=±5V/10K, or ±500ua. For a constant current into/out of a capacitor, V=I*T/C. In this case (for 50% duty cycle), Vpp=500ua*50usec/100nF, or Vpp=250mv. This is a sawtooth wave (a triangle if the duty cycle is 50%).<p>R2 and C2 are more easily analyzed in the frequency domain. They form a lowpass filter with a -3dB cutoff frequency of Fc=1/(2*pi*R2*C2)=159 Hz. This is about 6 octaves below 10kHz, and a single-pole RC filter falls at 6dB per octave, so we should get about 36dB attenuation of the fundamental of the sawtooth wave on C1 (the harmonics will be inconsequential). Since the amplitude of the fundamental of a triangle wave is about 81% of the peak-to-peak value, the output ripple will be about -36dB (0.0158) of 81% of 250mv, or about 3.2mv p-p. A simulation on SwitcherCAD III yielded 3.1mv p-p ripple. If you change the duty cycle in either direction, the ripple amplitude will be less than this.<p>That's how I analyzed this circuit. Synthesis is a little harder, and offhand I don't know how to do it in "closed form", but a little trial and error on paper will get you where you want to be pretty quickly.<p>Edit:
After thinking about this for about 10 seconds after I posted it, I realized that the whole filter can be analyzed as a 2-pole lowpass, with about 72dB of attenuation at 10kHz, which also yields 3.2mv of ripple. Duh!<p>Neither method addresses how to calculate the settling time, which may be what Beaker is most interested in.<p>[ December 03, 2004: Message edited by: RonH ]</p>

[redrocker]

Thanks RonH, but that was not what I was looking for. I wanted to be able to compute the steady-state DC value given the circuit, or conversely, be able to derive the appropriate component values given the frequency.<p>I wanted to have an analytical method of determining the component and frequency relationships, but I could not find a way, so instead I came up with a pattern relationship from the reference design.<p>1. The resistor values are the same as the frequency.
2. The time constant of the RC pair is 10 times the period of the waveform.<p>Given those two constraints, the capacitor value can be computed for a given frequency. The formula I derived is simply C = 10 / (f * R), where f = frequency in Hz, R = f = resistance in ohms.<p>I tried this for f=1000 Hz and for f=25000 Hz, and it seemed to work OK. This is a good little microcontroller circuit, because it's essentially a crude little D/A using PWM and common passive parts. However, it is not fast-changing, so it's not a replacement for demanding applications.

[rshayes]

The DC output level is proportional to the pulse voltage and the duty cycle. It does not depend on the filter design.<p>The filter design does change the ripple voltage in the output. The object is to make the ripple small enough that it is not significant.<p>The worst case for ripple is probable a 50% duty cycle square wave. The strongest component of this square wave will occur at the switching frequency, with weaker components at multiples of the switching frequency. In a square wave only the odd harmonics are present. As the duty cycle changes, energy will be transferred from odd harmonics into the even harmonics. In general, the harmonic energy decreases at the higher frequency harmonics.<p>Since the filter attenuation also increases with frequency, the component at the switching frequency is the strongest and the least attenuated. If the attenuation of this component is adequate, the attenuation of the other harmonics will probably cause their effect to be insignificant.<p>The filter that you describe will have a high frequency asymptote that passes through unity gain at about 159 Hz and decreases with the square of the frequency. At 10 KHz, the attenuation will be about 3956 times.<p>If the switching frequency is lowered, the attenuation would decrease, and the ripple would increase. This could be compensated for by increasing the capacitance or resistance values.<p>For example, decreasing the switching frequency to 5 KHz would increase the ripple by a factor of 4. Increasing the two resistors to 20K or increasing the two capacitors to .2 uF would compensate for this change.<p>[ December 04, 2004: Message edited by: stephen ]</p>

[redrocker]

Got it now. Thanks, stephen and RonH.