worlds largest IC

[jrz126]

In the news section of a N&V, I read something about the worlds largest IC. It was called MOOCOW or something like that (they gave a part # but i cant remember it). I was kinda curious about it so I tried searching online, but I couldnt find anything on it. <p>anyone have more info on this?

[jollyrgr]

APRIL FOOL!!!!!

[haklesup]

Good one. <p>But seriously, IBM is fooling around with devices with over 2500 pins and BGA packaged devices with 1200-1700 pins are now getting more common. These monsters are often SoC (System on a Chip)Telecommunication switching networks on a single chip. By the way, when you have so many pins on a package, often over half of them are ground and power pins. <p>As far as physical area is concerned, the largest chips are typically image sensors for satellites, spy planes, telescopes and the like and can be as large as the wafer they are manuafatured on but I doubt that anyone who would make such a sensor (military) would brag about it in public.

[dacflyer]

talk about wafers and dies etc.. i have looked deep into some of them chips etc mostly e-proms with windows..with 10x 30x scopes and all i see are etched lines etc, they make no sence to me as far a a real circuit would... how does one design a circuit like them and ever hope it to function...i know they obviously work...but i don't get it... all i see in the chip is lines like a maze,,with lots of dead ends... anyone got a super close up immage or some way for me to understand how a IC tics?

[haklesup]

One of the many (and first) jobs I have done while at my company was reverse engineering IC chips. I did many 1M DRAM/SRAM and the first Flash devices as well as some other interesting devices. The data was mostly used for patent infringement cases but occasionally a customer seemed to want to learn a few secrets.<p>In any case, you need at least 250X to 500X to get started and some structures in todays leading devices are too small to see with a light microscope that tops out around 1500x-1800x. You would need a SEM to see these clearly.<p>The RE process basically worked like this.<p>1. Take a bunch of IC devices and remove the package by dipping in 250C Sulphuric acid. Then deprocess a set (using cocktails of nasty acids and lapidary-like polishing techniques) to remove each metal layer so that the layers below could be clearly seen. Now I have 5-6 slides each with a device delayered to a different point (metal 1, metal 2, polysilicon and diffusion layers were most useful but other layers apply depending on process).<p>2. Take lots of high mag photos (poloroid at the time)of each layer and paste them together into several giant 1000x collages of the device that you can write on.<p>3. Use our propriatary adaptation to our SEM to scan the entire die into an image file and print onto strips of paper (dot matrix at the time) paste this up into a giant carpet sized image of the die (20'x20' was not unusual). We called this an "ultravision scan", this SEM did not have a digital image capture, we tapped right into the scan voltage and digitized our own image.<p>4. Crawl around on this scan for a few weeks and mark each and every metal trace with a node number with a pen. (a real challenge since the scans were notoriously low res)<p>5. Use the photos to mark out where each individual circuit "macro" begins and ends. Transfer this to the scan and mark input and output nodes. <p>6. Somewhere along the way you need to solve each Macro so you know what logic or function is associated with it (inverter, NAND, FF, many more). You do this by numbering each transistor (P and N types) and then sketcing the metal interconnects to make a transistor level schematic which is then transformed to a logic level symbol with input and output nodes labeled.<p>7. combine info from steps 4,5,6 to make a netlist.<p>8. Manually reverse the netlist into a coherent schematic you can deliver to the customer.<p>The whole process took about 3 months. At the end of each project, I could read circuits right off the metal lines like I was some kind of micro-archeologist reading hyroglyphics off king Tut's wall. Unfortunately, each designer/company/process has a different style so that knowledge only goes so far.<p>I liken the whole thing to an episode of "Batman" where Batman was assembling a puzzle face down as he was explaining to Robin how it sharpened his intellect or whatever. RE of an IC is like this because not only do you not know what it will look like ahead of time but you need to cut out each piece and draw the picture on each one before you can assemble it.<p>In some respects it would be easier to do this today because computers, imaging software and CAD programs are considerably more powerful but as the technology shrinks, much of what I did on an Olympus Light microscope would now need to be done in an SEM. Furthermore, devices with 3 or more metal layers are virtually impossible to see the essential structures without delayering (which is also more challenging due to the smaller size)<p>I shall post a few scans on my website in www.ultratest.com/NV of images of some simpler structures. (but not right away, check back later when I get my scanner working)

[haklesup]

OK I posted 3 examples in this fileRE Example<p>The solutions are in the file but to help you understand what you are looking at.<p>One picture os with the MEtal 1 level exposed, this shows most relevant interconnects but not supply contacts or macro to macro interconnects which were on metal 2 (removed) in this design.<p>The other photo is with just the Polysilicon and diffusion layers visable and this allows clear view orf the source/gate/drain areas of each transistor.<p>Source Drain are the small rectangles with the round dots (Metal-Si contacts) on them. The gates are the long smooth lines with one contact at the end.<p>In general, PMOS transistors are latger than the NMOS transistors so usually I used odd numbers for the Ps and even for the Ns. Inputs are labeled with numbers and usually come in on metal 1 (bottom layer of metal is kind of like the top layer of a PCB) to a polysilicon contat. Outputs come from a silicon/metal contact and are usually marked with letters on my pix. <p>First one is a NAND with inverting input, Second one is an edge triggered D Flip Flop and the third is a "Mask Wired ROM"<p>Hope this helps.
Chris<p>[ May 03, 2004: Message edited by: haklesup ]</p>

[jwax]

And to take a peek at some chip designers artwork:
http://micro.magnet.fsu.edu/creatures/index.html

[dacflyer]

WOW , what a awsome treat to see..seen some awsome fotos , was great !<p>i still do not understand too good how a endless maze creates a circuit,, but i know it works..<p>i might just have to find me a microscope and start looking into some chips for artwork

[Dave Dixon]

Hi all,
Here's an interesting site with microphotography of cool things the engineers added to their artwork. I think Homer Simpson is even on a chip!
Dave<p>I.C. artwork

[jollyrgr]

I'll ask this question here as someone might know the full story. Maybe it was only an Urban Legend but then again it might be real.<p>Back in the earily 1980's a company designed a certain chip. (I do not know what it was for.) In any case the engineer/drafts person either hid his/her name as part of the artwork or signed the artwork so that his/her name would be printed on ever die of that chip made. Not long after creating this chip and getting it to market a rival Asian company came up with a chip to do the exact same function. The engineering team reverse engineered the knock-off chip and found the original designer's signature reproduced on the die. Is this an UL or does anyone know the real story.

[Chris Smith]

Basically the way a chip works is they etch lines or paths in a pure silicon insulator called the chip or die where they want a connection, transistor, or a resistor etc to be,... using NM light technology to cut small groves and then dope or mask where they want traces of materials to be or not be, and these nanno structures of metals and exotic materials in the etched out areas are the actual transistors and components them self.

[Chris Smith]

Yes that story is semi true. A guy did sign his name in a chip.

[jwax]

Analogous to mapmakers that purposely put erroneous info on their maps. If Joe Blow decides to become a "mapmaker" by copying and selling those maps, he is jailed for infringement due to the "errors" that the real mapmaker added.
I fabricated semis before, and the way we "get small" is to reduce photographically the desired image. Take a picture of a picture, again and again, and that 24" drawing becomes .024" after 3 reductions of 10X each. Adding a "personal" touch is easy!

[haklesup]

Semiconductor patent law is very complex. You can have a patent on a circuit which protects you from any copy of the ckt no matter what it looks like. However, many circuits are so common that they cannot be patented (like an inverter or NAND gate). In this case the artwork used to produce the circuites is protected by Copyright law. In this case you would find a little M in a circle (instead of the c) which means Mask Copyright.<p>When ripping off a design by reverse engineering. You can take the high road and figure out the circuits and then create your own masks/artwork and if no patents are involved, this may be legal. Alternatively, you could take the low road and just photocopy the mask layers and reproduce the chip exactly. In this case it is straightforward for the copyright holder to identify characteristic shapes in the layers and prove their case. <p>Allowing the designers to put their initials on various mask layers (particularly top metal) is a common practice. Not so much to help catch copyright frauds but more as an ego boost for those engineers. However, show a non-active element of the artwork in court and the case is pretty well prooved.<p>Ive seen lots of initials on Intel and AMD chips but other companies put none. It's definately a company culture thing.<p>My collection of IC (on Die)logos includes a Dolfin, Sea Turtle, lightning bolt, state of Florida, State of Idaho with Moose head, State of Idaho with mountains (AMI-gould), A fish and some little bugs (not a logo but some ones idea of a joke)

[haklesup]

[QUOTE]Originally posted by haklesup:
[QB]Semiconductor patent law is very complex. You can have a patent on a circuit which protects you from any copy of the ckt no matter what it looks like. However, many circuits are so common that they cannot be patented (like an inverter or NAND gate). In this case the artwork used to produce the circuites is protected by Copyright law. In this case you would find a little M in a circle (instead of the c) which means Mask Copyright.<p>When ripping off a design by reverse engineering. You can take the high road and figure out the circuits and then create your own masks/artwork and if no patents are involved, this may be legal. Alternatively, you could take the low road and just photocopy the mask layers and reproduce the chip exactly. In this case it is straightforward for the copyright holder to identify characteristic shapes in the layers and prove their case. <p>Allowing the designers to put their initials on various mask layers (particularly top metal) is a common practice. Not so much to help catch copyright frauds but more as an ego boost for those engineers. However, show a non-active element of the artwork in court and the case is pretty well prooved.<p>Ive seen lots of initials on Intel and AMD chips but other companies put none. It's definately a company culture thing.<p>My collection of IC (on Die)logos includes a Dolfin, Sea Turtle, lightning bolt, state of Florida, State of Idaho with Moose head, State of Idaho with mountains (AMI-gould), A fish and some little bugs (not a logo but some ones idea of a joke)<p>ALso here are some photo contest winners from EDFAS (Electron Devices Failure Analysis Society)<p>EDFAS Photo Contest<p>You will need to click on the Photo Contest winners link on the left column of this page.