## Can't identify type of gate in diagram explaining inner

This is the place for any magazine-related discussions that don't fit in any of the column discussion boards below.
jalbers
Posts: 18
Joined: Tue Dec 18, 2001 1:01 am
Contact:

### Can't identify type of gate in diagram explaining inner

There is a really good graphical simulation of the inner worrkings of a 555 timer chip at http://www.williamson-labs.com/ under 555 on the
left frame.<p>However, I am trying to follow what is happening and think that I almost understand. I need some clarification of what type of logic gate is just before the Rst on the flip flop? It looks like an OR gate and the two little circles just in front look like inverters. If it is a straight OR gate, then I don't understand how the circuit
would work because pin 4 is always held high and this would force the Rst to always be high also. If the little circles are invertors, then I don't understand why both of them need to be there. I am also assuming that the flip flop is the traditional RS flip flop.<p>Any help would be greatly appreciated.<p>Thank You

Bob Scott
Posts: 1192
Joined: Wed Nov 20, 2002 1:01 am
Location: Vancouver, BC
Contact:

### Re: Can't identify type of gate in diagram explaining inner

John,<p>It took me a few years to realize that engineers sometimes draw inverting circles on the inputs of gates instead of the outputs because they don't want to confuse negative and positive logic.<p>The OR gate with 2 circles on the inputs is equivalent to a NAND gate. An AND gate with inverting symbols on the inputs is equivalent to a NOR gate. In negative logic you can use positive logic chips but positive logic OR gates become negative logic AND gates, and vice versa. (Check the truth tables.)<p>Note: If you click on "animation", the schematic for the internal workings for the 555 changes. There is an error in this drawing. In this animation version the lower comparator is drawn with the "+" and "-" terminals reversed. Anyone could get confused trying to figure out the erroneous diagram.<p>Geez, I keep finding more errors. The bubble on the upper input to the or gate coming from the output of the upper comparator should be removed. Whoever drew these diagrams should have stayed in bed that day.<p>Bob<p>[ April 28, 2004: Message edited by: Bob Scott ]<p>[ April 29, 2004: Message edited by: Bob Scott ]<p>[ April 29, 2004: Message edited by: Bob Scott ]<p>[ April 29, 2004: Message edited by: Bob Scott ]</p>
-=VA7KOR=- My solar system includes Pluto.

### Who is online

Users browsing this forum: Google [Bot] and 39 guests