Some Occilator Help

[billdar]

Hello all, this is a horribly specific question.. but you all have an amazing depth for this stuff.<p>Im using an Sigmatel STAC9753 codec for a sound device I am making.<p>Im having trouble getting 2 things.<p>1. I can't seem to get the internal PLL to lock on a digital signal (the data sheet doesn't specify in-put clock)<p>2. I can't seem to get my 25Mhz quartz crystal to occilate... at all. I am using it with 2 27pf caps for tuning, and I still don't get anything.<p>Any Ideas?<p>Thanks,
Bill

[Edd]

Bill:
Assuming you're rounding off the 24.756 xtal ref to 25. And using a typically chip manuf spec'd unit, as other specific cuts activity/start up can be quite quarrelsome at low Vcc levels ....like your 3.3 supply.
To be using a common data sheet reference consult/confirm :
http://extranet.sigmatel.com/library/au ... ds-3-1.pdf
As per Para 3.2.4 on page 18..... are those connectiions in compliance ?
Looks like in their [Unit Under Test] evaluation they are sampling at 48khz and Bit clocks @ 12.288 Mhz.
Also you might look at other parts of the documentation, as they are giving some flow chart/ troubleshooting info.<p>73's de Edd
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[email protected]...(Firewalled-Spam*Cookies*Crumbs)<p>[ January 25, 2003: Message edited by: Edd Whatley ]</p>

[billdar]

Yeah, you were correct about my rounding <p>And yeah, I have tried each of the settings with
different input clocks. About 20 or so combos
tried...<p>Pretty much what I am trying is to feed the Xtalin
a digital clock. Its convienient because I have
this big 'ol multi-frequency clock generator on
board.<p>The problem I'm seeing is that the bit_clock is
not locking and is swaying between 7.3-7.5MHz with
a very nasty looking waveform. Like a 'before'
picture in a signal integrity book.<p>What I'm thinking, is that if the codec uses an
analog pll to generate bit_clk from the xtal_in
that maybe the high frequency components of the
digital clock are preventing a lock at 12.28Mhz.<p>It's just a theory, because I see a lot of info on
the bit_clock, but not much on the xtal_in like
jitter, drive current, impedance, max/min
voltages....<p>This lends to my second problem of not being able
to get my little 24.576 crystal to occilate to
see if inputing a nice sine wave will clean up the
bit clock.<p>Either way... thanks for the input and getting me
to re-read the specs again

[Timothy Rasch]

Hi , try changing 27 pf caps to slightly smaller value 15pf or 12pf[loading of crystal could be the problem or biasing between the pins of ic for linear operation]. Also measure between pins of ic where crystal goes the resistance with a digital meter with the power off.It should be 10meg to 22 meg for a cmos ic. I don't know what your Ic does completely.It seems to me it is a PLL,crystal osc, programable counter. Note to see crystal oscillator on oscilloscope use only a 10:1 probe so you don't load down the crystal circuit. Also note cmos crystal oscillators must work at a higher voltage than 3.3v .See your spec sheet first for the typical voltage [which is 10v for most cmos crystal oscillators]. Good luck!! Tim Rasch [email protected]

[Edd]

Bill:
So your occilator still doesn’t want to oscillate ! Me, I used to make ossifriers.Hi!<p>Referring to page 21 as per ref above:
…to me that pin 1 & 2 circuitry just doesn’t look right on the data sheet. I’m always seeing the time base element in a hi Z closed loop circuit. Now if you are going for EXT sig input that coupling/isolation res on #1 and pin #2to Gnd configuration seems in agreement. I believe that they left the DS marked up that way, typically I’d expect to see the dot to the resistors (0 ohm) for the grounding of the xtal on bottom #2 and the dot to the input/isolation resistor to be missing and those components being nonexistent.Of course, this being when an xtal is utilized as ur time base element. Check it out that way..<p>Referring to page 85 on your devices pin 48 status…pulled up or pulled down, but not floating….right ?<p>On osc xtal circuitry loading via ancillary test equipment….Just monitor down at pin 6 (div 2 output)….plenty of buffering and a hefty sig level at that point.<p>No problem in CMOS osc design in that electronic watch on your arm, working at 1.5-3Vdc supply levels, but on the xtal, it’s the cut.<p>73's de Edd
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<p>[ January 27, 2003: Message edited by: Edd Whatley ]</p>