74hc595 noise problem ?

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Deion Adel
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74hc595 noise problem ?

Post by Deion Adel »

Hi
in our project we connecting 25 , 74hc595 to each other and shifting data on them
but suddenly we have some undesired result with the output of the 74hc595
i want to know what kind of noise consideration should i take into account for
connecting these numers of 74hc595 to each other ? 74hc595 datasheet
plz help me
Thanks
dyarker
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Re: 74hc595 noise problem ?

Post by dyarker »

How did you connect them?
What is undesired result?
What kind power supply, and did you use distributed surge suppression capacitors?
Dale Y
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haklesup
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Re: 74hc595 noise problem ?

Post by haklesup »

HC logic is pretty easy to work with, it has wide input and output logic levels and if you are using all the same kind, its probably not a logic level issue anyway.

You should always place decoupling capacitors close to the VDD and GND pins of each logic device (small ceramic values) and a larger capacitor near where the power supply enters (larger Electrolytic values) 470pf and 47 uF is a good place to start but the actual value is not critical. Survey some logic schematics online and imitate the range of values used.

The small cap close to the device shunts(decouples) noise (fluctuations in IDD that can cause VDD to fluctuate) created by that device to ground so it does not contaminate other devices. The larger cap filters noise (any source) from power entering the circuit.

74HC family of logic will have IDDQ (quiescent) close to 0 if all inputs are static but each device can consume up to 3mA transiently when the input or output is toggling between logic levels. This high transient IDD makes the 74HC and 74HCT families of 5V logic quite noisy when operated at high speed. You might find it quieter to implement in newer 3.3V logic families built on smaller features, they will have smaller switching transients. IDD switching transients are universal to all CMOS input only pins but in newer technologies, it will be less pronounced.

Another tip with 74HC logic is never ever leave any inputs floating, it will act like the input is biased to 1/2 logic level and increase IDDQ supply current for each and every input left floating. Tie high or low as your design requires. You can float unused outputs without issue.
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