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I use RLC meter to measure the impedance of analog input of AD9057.
Because the input bandwidth is from 32MHZ to 48MHZ, i measure 101-240j(32MHZ), 69-206j(40MHZ), 50-173j(48MHZ), respectively.
I'd like to design a match circuit that can transfer input impedance at all bandwidth(32-48MHZ) to ideal 50OHM as possible.
Does anybody can help me to design it?

I don't know your application or this chip, but I assume this is an A/D chip. Typically A/D chips are very high impedance -- much higher than what you measured.<p>Also, you should be clear as to why you are trying to match impedances. One reason is to maximize power transfer to a load. However, for this you can only match the load to the source; I don't think you ever want to match the source to the load, since lowering the souce impedance will always improve power transfer no matter what the load is. Anyway, with an A/D chip, power tranfer is not an issue.

The Analog Devices data sheet gives the input impedance as typically 150K ohms paralleled by 2 pF. Your measurements imply a shunt capacitance of about 20 pF, which is about a factor of ten too high. The conductance values that you measured are even farther out of line.<p>The measurement may have been done at too high a level. This will forward bias the protection diodes on the input and make the input impedance seem lower. There may be a fair amout of stray capacitance in your test setup. At 48 MHz, practically any lead length is too much for an accurate measurement.<p>The basic requirement is that the source impedance that the input is driven from should be low enough that the 2 pF capacitance will cause negligable amplitude error or phase shift. Something in the 100 ohm region may be low enough, and this can be done with a reasonably fast transistor in an emitter follower. A terminated 50 ohm transmission line would present a source impedance of 25 ohms, and this would probably be low enough. Look at figure 7 (evaluation board schematic) on the AD9057 data sheet.